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d a t a sh eet preliminary speci?cation file under integrated circuits, ic01 may 1994 integrated circuits philips semiconductors saa3323 drive processor for dcc systems
may 1994 2 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 features operating supply voltage: 2.7 to 3.6 v low power dissipation: 84 mw (typ) single chip digital equalizer, tape formatting and error correction 8-bit flash analog-to-digital converter (adc) for low symbol error rate two switchable infinite impulse-response (iir) filter sections 10-tap finite impulse-response (fir) filter per main data channel, with 8 bit coefficients, identical for all main channels 10-tap fir filter for the aux channel analog and digital eye outputs interrupt line triggered by internal auxiliary envelope processing e.g. label, counter, and others robust programmable digital pll clock extraction unit low power sleep mode slew rate limited electromagnetic compatibility (emc) friendly output digital compact cassette (dcc) optimized error correction programmable symbol synchronization strategy for tape input data microcontroller control of capstan servo possible during playback and recording frequency and phase regulation of capstan servo during playback choice of dynamic random access memory (dram) and static random access memory (sram) types for system random access memory (ram) scratch pad ram for microcontroller in system ram integrated interface for precision adaptive sub-band coding (pasc) data bus three wire microcontroller l3 interface protection against invalid auxiliary data seamless joins between recordings. general description the saa3323 performs the drive processor function in the dcc system. this function is built up of digital equalizer, error correction and tape formatting functions. the digital equalizer is intended for use with dcc read amplifiers tda1318 or tda1380. the tape formatting and error correction circuit is intended for use with pasc ics saa2003 and saa2013, and write amplifiers tda1319 or tda1381. ordering information note 1. when using reflow soldering it is recommended that the dry packing instructions in the quality reference pocketbook are followed. the pocketbook can be ordered using the code 9398 510 34011. type number package pins pin position material code SAA3323H 80 tqfp80 (1) plastic sot315-1 saa3323gp 80 qfp80 (1) plastic sot318-2
may 1994 3 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 block diagram fig.1 block diagram. (1) fir = finite impulse-response. (2) iir = infinite impulse-response. handbook, full pagewidth digital- to-analog converter mlb761 saa3323 phase locked loop zero crossing fir (1) iir (2) auxiliary envelope detection analog to-digital converter tape input buffer error corrector ram interface internal data bus sub-band i s interface 2 sbws sbcl tape output buffer control interface 811 6 equalizer module sbda sbef sbmclk sbdir d0 to d7 a0 to a10 a11 to a16 wen oen pino1 pino2 pini l3int l3mode l3clk l3data sleep reset urda speed rdmux rdsync anaeye wdata tclock v ref(p) v ref(n) l3ref bias
may 1994 4 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 pinning symbol pin description type (1) qfp80 tqfp80 sbws 1 79 word select for sub-band pasc interface i/o (1 ma) sbcl 2 80 bit clock for sub-band pasc interface i/o (1 ma) sbda 3 1 data line for sub-band pasc interface i/o (1 ma) sbdir 4 2 direction line for sub-band pasc interface o (1 ma) sbmclk 5 3 master clock for sub-band pasc interface i urda 6 4 unreliable data o (1 ma) l3mode 7 5 mode line for l3 interface i l3clk 8 6 bit clock line for l3 interface i l3data 9 7 serial data line for l3 interface i/o (2 ma) l3int 10 8 l3 interrupt output o (1 ma) v dd1 11 9 digital supply voltage s v ss1 12 10 digital ground s l3ref 13 11 l3 bus timing reference o (1 ma) reset 14 12 reset saa3323 i sleep 15 13 sleep mode selection of saa3323 i clk24 16 14 24.576 mhz clock input i azchk 17 15 channel 0 and channel 7 azimuth monitor o (1 ma) mclk 18 16 6.144 mhz clock output o (1 ma) test3 19 17 test3 output; do not connect o (1 ma) ercostat 20 18 erco status, for symbol error rate measurements o (1 ma) oen 21 19 output enable for ram o (2 ma) a10/ ras 22 20 address sram; ras dram o (2 ma) v dd2 23 21 digital supply voltage s v ss2 24 22 digital ground s d7 25 23 data sram i/o (4 ma) d6 26 24 data sram i/o (4 ma) d5 27 25 data sram i/o (4 ma) d4 28 26 data sram i/o (4 ma) d3 29 27 data sram; data dram i/o (4 ma) d2 30 28 data sram; data dram i/o (4 ma) d1 31 29 data sram; data dram i/o (4 ma) v dd7 32 30 digital supply voltage for ram s v ss7 33 31 digital ground for ram s d0 34 32 data sram; data dram i/o (4 ma) a0 35 33 address sram; address dram o (2 ma) a1 36 34 address sram; address dram o (2 ma) a2 37 35 address sram; address dram o (2 ma) a3 38 36 address sram; address dram o (2 ma)
may 1994 5 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 a4 39 37 address sram; address dram o (2 ma) v ss3 40 38 digital ground s v dd3 41 39 digital supply voltage s a5 42 40 address sram; address dram o (2 ma) a6 43 41 address sram; address dram o (2 ma) a7 44 42 address sram; address dram o (2 ma) a12/pino5 45 43 address sram; port expander output 5 o (2 ma) a14/pino1 46 44 address sram; port expander output 1 o (2 ma) a16/pino3 47 45 address sram; port expander output 3 o (2 ma) a15/pino4 48 46 address sram; port expander output 4 o (2 ma) wen 49 47 write enable for ram o (2 ma) a13/pino2 50 48 address sram; port expander output 2 o (2 ma) a8 51 49 address sram; address dram o (2 ma) v dd4 52 50 digital supply voltage s v ss4 53 51 digital ground s a9/ cas 54 52 address sram; cas for dram o (2 ma) a11 55 53 address sram o (2 ma) speed 56 54 pulse width modulation (pwm) capstan control output for deck o t (1 ma) pino2 57 55 port expander output 2 o t (1 ma) wdata 58 56 serial output to write ampli?er o (1 ma) tclock 59 57 3.072 mhz clock output for tape i/o o (1 ma) v ss5 60 58 digital ground s v dd5 61 59 digital supply voltage s test2 62 60 test mode select; do not connect i pd rdmux 63 61 analog multiplexed input from read ampli?er i a v ref(p) 64 62 adc positive reference voltage i a v ref(n) 65 63 adc negative reference voltage i a substr 66 64 substrate connection i a bias 67 65 bias current for adc i a v ssa 68 66 analog ground s v dda 69 67 analog supply voltage s anaeye 70 68 analog eye pattern output o a rdsync 71 69 synchronization output for read ampli?er o (1 ma) v dd6 72 70 digital supply voltage s v ss6 73 71 digital ground s chtst1 74 72 channel test pin 1 o (1 ma) chtst2 75 73 channel test pin 2 o (1 ma) test0 76 74 test mode select; do not connect i pd test1 77 75 test mode select; do not connect i pd symbol pin description type (1) qfp80 tqfp80
may 1994 6 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 note 1. i = input; i a = analog input; i pd = input with pull-down resistance; i/o = bidirectional; o = output; o a = analog output; o t = 3-state output; s = supply. pini 78 76 port expander input i pino1 79 77 port expander output 1 o (1 ma) sbef 80 78 sub-band pasc error ?ag line o (1 ma) symbol pin description type (1) qfp80 tqfp80 fig.2 pin configuration (sot315-1; tqfp80). handbook, full pagewidth 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 76 75 74 73 72 71 70 69 68 67 66 65 77 25 26 27 29 30 31 32 33 34 35 36 37 38 39 40 28 21 22 23 24 64 63 62 61 saa3323 tclock wdata pino2 v ss4 v dd4 a8 a15/pino4 a16/pino3 a7 a6 a12/pino5 a14/pino1 wen a13/pino2 a9/cas v ss5 speed a11 mlb762 a5 v dd3 a10/ras oen d5 d4 d3 d2 d1 d0 a0 a1 a2 a3 a4 v ss3 v dd7 v ss7 v ss2 v dd2 d6 d7 l3mode l3clk l3data l3int reset v ss1 v dd1 azchk ercostat test3 mclk sbws sbcl clk24 sleep l3ref urda sbmclk sbdir sbda rdmux test2 anaeye rdsync chtst1 chtst2 test0 test1 sbef bias substr pini pino1 v ref(n) v ref(p) v dd5 ss6 v dd6 v dda v ssa v
may 1994 7 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 fig.3 pin configuration (sot318-2; qfp80). handbook, full pagewidth 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 25 26 27 29 30 31 32 33 34 35 36 37 38 39 40 28 80 79 78 76 75 74 73 72 71 70 69 68 67 66 65 77 saa3323 l3mode l3clk l3data l3int reset v ss1 v dd1 azchk d7 d6 ercostat a10/ras test3 mclk rdmux test2 tclock wdata pino2 v ss4 v dd4 a8 a15/pino4 a16/pino3 a7 a6 a12/pino5 a14/pino1 wen a13/pino2 a9/cas d5 d4 d3 mlb763 anaeye rdsync chtst1 chtst2 test0 test1 v dda v ssa sbef sbws sbcl bias substr v dd6 v ss6 pini pino1 d2 d1 d0 a0 a1 a2 a3 a4 a5 v dd3 v ss3 v dd7 v ss7 clk24 sleep oen l3ref urda sbmclk sbdir sbda v ref(n) v ref(p) v ss5 v dd5 speed a11 v ss2 v dd2
may 1994 8 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 functional description handbook, full pagewidth mbd620 tape drive processing dac tda1305 adc saa7366 analog output digital audio i/o tda1315 iec958 analog input audio in/out pasc processor i s 2 l r l r sfc3 saa2003 stereo filter codec adas3 saa2013 adaptive allocation filtered i s 2 sub-band i s 2 baseband drp saa2023 or saa3323 drive processor ram 41464 buffer 64k x 4 rdamp tda1380 read amp. wramp tda1381 write amp. fixed head tape capstan drive speed control mechanics drivers analog cc l output analog cc r output system microcontroller system control search data detect switch fig.4 dcc system block diagram.
may 1994 9 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 a simplified block diagram of the saa3323 is shown in fig.1. dcc drive processing the saa3323 provides the following functions for the dcc drive processing. p layback modes analog-to-digital conversion tape channel equalization tape channel data and clock recovery 10-to-8 demodulation data placement in system ram c1 and c2 error correction decoding interfacing to sub-band serial pasc interface interfacing to microcontroller for sysinfo and aux data capstan control for tape deck. r ecord modes interfacing to sub-band serial pasc interface c1 and c2 error correction encoding formatting for tape transfer 8-to-10 modulation interfacing to microcontroller for sysinfo and aux data capstan control for tape deck, programmable by microcontroller. s earch mode detection and interpretation of aux envelope information aux envelope counting search speed estimation. tape formatting and error (tfe) correction module the tfe module has 3 basic modes of operation as shown in table 1. table 1 basic modes of tfe module. tfe registers the tfe module has 8 writable and 5 readable registers that are accessible via the l3 interface, one write register (cmd) and four read registers (status0 to status3) which are directly addressable, the other registers are indirectly addressable via commands sent to the cmd register. the registers are named as shown in table 2. table 2 tfe register names. note 1. the 4 lsbs of register set3 set ram type (rtype) and ram timing (rtim). see table 3. for normal operation the 4 msbs of register set3 should be logic 0. mode explanation dpap audio and sysinfo (main data) play; aux play dpar audio and sysinfo (main data) play; aux record drar audio and sysinfo (main data) record; aux record register name read/write cmd w status0 r status1 r status2 r status3 r set0 w set1 w set2 w set3 (1) w spddty w bytcnt w raccnt w speed r
may 1994 10 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 table 3 ram settings by register set3. tfe data streams the tfe module has three read/write data streams that are accessible via the l3 interface and they are shown in table 4. ram register set3 rtype 0 bit 0 rtype 1 bit 1 rtim 0 bit 2 rtim 1 bit 3 table 4 tfe data streams. tfe commands these are the commands that need to be sent to the tfe in order to access the indirectly accessible registers and the data streams, see table 5. data stream name read/write sysinfo r/w auxinfo r/w scratch pad ram r/w table 5 tfe commands. name command byte explanation 76543210 rdspeed 00000000 read speed register ldset0 00010000 load new tfe settings register 0 ldset1 00010001 load new tfe settings register 1 ldset2 00010010 load new tfe settings register 2 ldset3 00010011 load new tfe settings register 3 ldspddty 00010101 load spddty register ldbytcnt 00010111 load bytcnt register ldraccnt 00011000 load raccnt register rdaux 00100000 read auxiliary information rdsys 00100001 read sysinfo rddrac y z 100010 read ram data bytes (8 bits) from quarter yz rdwdrac y z 100011 read ram data words (12 bits) from quarter yz wraux 00110000 write auxiliary information wrsys 00110001 write sysinfo wrdrac y z 110010 write ram data bytes (8 bits) to quarter yz wrwdrac y z 110011 write ram data words (12 bits) to quarter yz digital equalizer module the digital equalizer module has 2 basic modes of operation as shown in table 6. table 6 basic modes of equalizer module. mode explanation play main data and aux channels are equalized search only aux channel is processed; aux envelope information is processed d igital equalizer registers the digital equalizer module has 9 write only, 3 read only and 1 read/write register(s) that are accessible via the l3 interface, one write register (cmd) and 2 read registers (status0 and status1) which are directly addressable, the other registers are indirectly addressable via commands sent to the cmd register. the registers are named as shown in table 7.
may 1994 11 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 table 7 digital equalizer register names. register name read/write cmd w status0 r status1 r coefcnt w fctrl w cht1sel w cht2sel w anaeye w aec r/w sspd r intmask w deq2set w clkset w d ata streams the digital equalizer module has one write only and one read only data stream that are accessible via the l3 interface and they are shown in table 8. table 8 digital equalizer data streams. d igital equalizer commands these are the commands that need to be sent to the digital equalizer in order to access the indirectly accessible registers and the data streams. data stream name read/write fir coef?cients to buffer bank w fir coef?cients from active bank w table 9 digital equalizer commands. table 10 filter control register. note 1. m cs is a microcontroller controlled coefficient bank switch. this causes the filter coefficients to be activated at a time that is safe for the digital equalizer, i.e. at the end of the fir program and that the complete value of coefficient number 9 has been received. name command byte explanation 76543210 wrcoef 0 0 1 1 0 0 0 0 write fir coef?cients to the digital equalizer buffer bank rdcoef 0 0 1 0 0 0 0 0 read fir coef?cients from the digital equalizer active bank ldcoefcnt 0 0 0 1 0 0 1 1 load fir coef?cient counter ldfctrl 0 0 0 1 0 1 0 0 load ?lter control register ldt1sel 0 0 0 1 0 1 1 0 load chtst1 pin selection register ldt2sel 0 0 0 1 0 1 1 1 load chtst2 pin selection register ldtaeye 0 0 0 1 1 0 0 0 load anaeye channel selection register ldaec 0 0 0 1 1 0 0 1 load aec counter rdaec 0 0 1 0 0 0 1 0 read aec counter rdsspd 0 0 1 0 0 1 0 0 read search speed register ldintmsk 0 0 0 1 0 0 1 0 load interrupt mask register lddeq3set 0 0 0 1 0 0 0 0 load digital equalizer settings register ldclkset 0 0 0 1 0 0 0 1 load pll clock extraction settings register bit 765432 1 0 meaning ---m cs (1) sh1 sh0 reserved default 0 0 0 0 1 0 1 1
may 1994 12 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 table 11 sh1 and sh2 (fir output scaling). transfer of fir coef?cients for the main data channels (tracks 0 to 7) there are 10 coefficients (taps) each of 8 bits, where all of the data channels make use of the same coefficients. the addresses for the main data coefficients 0 to 9 are 0to9 dec respectively. there are ten coefficients (taps) each of 8 bits for the aux channel (chaux). the addresses for the auxiliary coefficients 0 to 9 are 16 to 25 dec respectively. sh effect on fir output 10 0 0 fir mod 256 01 mod 256 10 mod 256 11 mod 256 fir 2 ---------- fir 4 ---------- fir 8 ---------- there are 2 banks of coefficients for both the aux and the main data channels, namely the buffer, and the active banks. the microcontroller writes only to the buffer banks, and reads only from the active banks. the microcontroller can poll the digital equalizer status bit bksw to see when the switch occurs. bksw starts life low, goes high as a result of the bank switching and goes low as result of the complete value of a main data coefficient being received by the digital equalizer. the microcontroller sets m cs high before sending the new set of aux or main data coefficients, the digital equalizer resets it once the bank switch occurs. the actual fir coefficients that are used are a function of the tape head, read amplifier and type of tape (i.e. pre-recorded or own recorded) used, such information is outside of the scope of this data sheet. coef?cient address counter (coefcnt) this 5 bit counter is used to point to the fir coefficient to be transferred to or from the digital equalizer. table 12 coef?cient address counter. bit 765432 1 0 meaning --- cc4 cc3 cc2 cc1 cc0 default 0 0 0 0 0 0 0 0 pin explanations and interfacing to other hardware reset this is an active high input which resets the saa3323 and brings it into its default mode, dpap. this reset does not affect the contents of the fir filter coefficients in the digital equalizer. this should be connected to the system reset, which can be driven by the microcontroller. the duration of the reset pulse should be at least 15 m s. sleep this pin is an active high input which puts the saa3323 in a low power consumption sleep mode. this pin should be connected to the dcc sleep signal, which can be driven by the microcontroller. the clk24 clock may be stopped and the vrefp and vrefn inputs brought to ground while the saa3323 is in sleep mode to further reduce power consumption. when recovering from sleep mode, the sleep pin should be taken low and the saa3323 reset. clk24 this is the 24.576 mhz clock input and should be connected directly to the saa2003 (pin clk24). sub-band serial pasc interface connections the timing for the sub-band serial pasc interface is given in figs 5 to 7.
may 1994 13 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 handbook, full pagewidth mgb381 sbcl(in) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sbws(in) sbda(in) sbcl(in) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 sbws(in) sbda(in) v ih v oh sbcl(in) sbws(in) sbda(in) v ih v oh v ih v oh bit number 2 x t 40 ns mclk 40 ns fig.5 sub-band serial pasc interface timing; drar mode.
may 1994 14 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 handbook, full pagewidth sbcl(out) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sbws(out) sbda(out) sbcl(out) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 sbws(out) sbda(out) bit number sbef(out) sbef(out) mgb382 sbcl(out) sbws(out) sbda(out) sbda(out) v oh v ol v oh v ol sbmclk(in) v il ih v v oh v ol v oh v ol 60 ns 7 ns 7 ns fig.6 sub-band serial pasc interface timing in play modes; drpmas = logic 1.
may 1994 15 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 handbook, full pagewidth sbcl(in) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sbws(in) sbda(out) mgb383 sbcl(in) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 sbws(in) sbda(out) sbcl(in) sbws(in) sbda(out) bit number sbef(out) sbef(out) sbda(out) 40 ns t (40 40) ns mclk mclk t (40 85) ns v il ih v v oh v ol v oh v ol v il ih v 2 x t 40 ns mclk fig.7 sub-band serial pasc interface timing in play modes; drpmas = logic 0. sbmclk this is the sub-band master clock input for the sub-band serial pasc interface. the frequency of this signal is nominally 6.144 mhz. when the saa3323 is used with saa2003 this pin is tied to ground, and the tfe settings bit drpmas set to logic 1. sbdir this output pin is the sub-band serial pasc bus direction signal, it indicates the direction of transfer on the sub-band serial pasc bus. this pin connects directly to the sbdir pin on the saa2003. the transfer directions are shown in table 13. table 13 pasc bus transfer directions. sbdir direction 1 saa3323 to saa2003 transfer (audio play) 0 saa2003 to saa3323 transfer (audio record) sbcl this input/output pin is the bit clock line for the sub-band serial pasc interface to the saa2003. when used with saa2003 this pin is input only. it has a nominal frequency of 768 khz. sbws this input/output pin is the word select line for the sub-band serial pasc interface to the saa2003. when used with saa2003 this pin is input only. it has a nominal frequency of 12 khz. sbda this input/output pin is the serial data line for the sub-band serial pasc interface to the saa2003. sbef this active high output pin is the error-per-byte line for the sub-band serial pasc interface to the saa2003.
may 1994 16 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 urda this active high output pin indicates that the main data (audio), the sysinfo and the auxiliary data are not usable, regardless of the state of the corresponding reliability flags. the state of this pin is reflected in the urda bit of status byte 0, which can be read by the microcontroller. this pin should be connected directly to the urda pin of the saa2003. urda goes active as a result of a reset, a mode change from mode drar to dpap, or if the saa3323 has had to re-synchronize with the incoming data from tape. the position of the first sub-band serial pasc bytes in a tape frame is shown in figs 8 and 9. fig.8 position of first sub-band serial pasc bytes in a tape frame in dpap/dpar mode. handbook, full pagewidth snum sbws 'first byte" sbda byte 0 byte 1 byte 2 0 1 l3ref mgb384 handbook, full pagewidth snum sbws 'first byte' sbda byte 0 byte 1 byte 2 30 l3ref mgb385 fig.9 position of first sub-band serial pasc bytes in a tape frame in drar mode.
may 1994 17 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 ram connections the saa3323 has been designed to operate with drams and srams. suitable drams are 64k 4-bit or 256k 4-bit configurations operating in page mode, with an access time of 80 to 100 ns. the timing for read, write and refresh cycles for drams is shown in figs 10 to 12. the timing for srams is shown in figs 13 to 19. for fast srams: (these values are subject to verification during characterization in). the conditions (most critical at the required v dd ) are shown in table 14. table 14 fast sram conditions. note 1. the saa3323 should work in: rtype = 01; rtim = 00 mode. a9/ cas when saa3323 is used with sram this output pin is address line 9, and should be connected directly to the corresponding address pin on the sram. when saa3323 is used with dram this output pin is the column address strobe (active low), it connects directly to the column address strobe pin of the dram. a10/ ras when saa3323 is used with sram this output pin is address line 10, and should be connected to the corresponding address pin of the sram. when saa3323 is used with dram this output pin is the row address strobe (active low), it connects directly to the row address strobe pin of the dram. condition (1) time write pulse duration t w 140 ns data set-up to rising wen t su 72 ns write cycle time t cy 200 ns read access time t acc 240 ns oen this output pin is the output enable (active low) for the ram, it connects directly to the output enable pin of the ram. wen this output pin is the write enable (active low) for the ram, it connects directly to the write enable pin of the ram. a0 to a8 when saa3323 is used with dram these output pins are the multiplexed column and row address lines. when the 64k 4-bit dram is used, pins a0 to a7 should be connected to the dram address input pins, and pin a8 should be left unconnected. when using the 256k 4-bit dram the address pins a0 to a8 should be connected to the address input pins of the dram. when saa3323 is used with sram these are the lower address pins and should be connected directly to the sram address pins. a11 this output pin is the an address pin for the sram and when sram is used they should be connected directly to the address pins of the sram. when dram is used this pin should not be connected. a10 and a12 to a16 these output pins are the upper address pins for the sram and when sram is used they should be connected directly to the address pins of the sram. when dram is used or when the small sram is used all or some of these pins become available as port expander outputs.
may 1994 18 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 table 15 port expander outputs. d0 to d3 when saa3323 is used with sram these i/o pins form the lower nibble of the data bus connection to the ram, and should be connected to the corresponding data i/o pins of the sram. when saa3323 is used with dram these input/output pins are the data lines for the ram, they should be connected directly to the dram data i/o pins. d4 to d7 these input/output pins are the upper nibble of the data bus for use with sram, and when sram is being used they should be connected directly to the corresponding sram i/o pins. pin name pin port expander output conditions qfp80 tqfp80 a14/pino1 46 44 pino1 rtype = 00 a13/pino2 50 48 pino2 rtype = 00 a16/pino3 47 45 pino3 rtype = 00 or rtype = 01 a15/pino4 48 46 pino4 rtype = 00 or rtype = 01 a12/pino5 45 43 pino5 rtype = 00 fig.10 dram read cycle timing. handbook, full pagewidth wen a0 to a8 oen a10/ras d0 to d3 a9/cas t rp t ras t asr t rah mgb386 t rcd t oez t off t cas t cp t cah t cac t rac t asc nibble 0 data nibble 1 data nibble 2 data row address column address column address column address
may 1994 19 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 fig.11 dram write cycle timing. handbook, full pagewidth wen a0 to a8 a10/ras d0 to d3 a9/cas t rp t ras t asr t rah mgb387 oen t rcd t cas t cp t cah t dh t asc t wcs t wch t ds row address column address column address column address nibble 1 data nibble 0 data nibble 2 data fig.12 dram refresh cycle timing. handbook, full pagewidth wen a0 to a8 oen a10/ras d0 to d3 a9/cas t rp t ras t asr t rah mgb388 row address
may 1994 20 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 fig.13 fast sram read cycle timing. handbook, full pagewidth wen oen a0 to a16 d0 to d7 mgb389 t aa read t ohz read t oh t olz address address data data fig.14 fast sram write cycle timing; rtim = 00. handbook, full pagewidth wen oen a0 to a16 d0 to d7 t aw mgb390 t dw1 t dh1 write t wp wc t t dh2 read modify write t wp t dw2 t aa t ohz t olz t dho1 address address data data data
may 1994 21 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 fig.15 fast sram write cycle timing; rtim = 01. handbook, full pagewidth wen oen a0 to a16 d0 to d7 t aw mgb391 t dw1 t ddh write t wp wc t t ddh read modify write t wp t dw2 t aa t ohz t olz t dho1 t dah t dah address address data data data fig.16 fast sram write cycle timing; rtim = 10. handbook, full pagewidth wen oen a0 to a16 d0 to d7 t aw mgb392 t dw1 t dh1 write t wp wc t t dh2 read modify write t wp t dw2 t aa t ohz t olz t dho1 t woa address address data data data
may 1994 22 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 fig.17 fast sram write cycle timing; rtim = 11. handbook, full pagewidth mgb393 a0 to a16 d0 to d7 oen wen write read modify write fig.18 slow sram read cycle timing. handbook, full pagewidth wen oen a0 to a16 d0 to d7 t aa t ohz mgb394 t olz t oh read read address address data data
may 1994 23 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 fig.19 slow sram write cycle timing. handbook, full pagewidth wen oen a0 to a16 d0 to d7 t aw mgb395 t dw1 t dh write t wp wc t t aw t dh write t wp wc t t dw2 address address data data table 16 timing values for figs 10 to 12. symbol value (ns) t rp 3 110 t ras 3 510 t rcd 3 70 t cp 3 30 t cas 3 100 t asr 3 100 t rah 3 25 t asc 3 30 t cam 3 100 t ds 3 25 t dh 3 100 t wcs 3 30 t wch 3 100 t rac 160 t cac 80 table 17 timing values for figs 13 to 17. table 18 timing values for figs 18 and 19. symbol value (ns) t wp 3 140 t aw 3 180 t wc 3 200 t dw 3 72 t dm 3 25 t aa 240 t hc 3 250 symbol value (ns) t wp 3 225 t aw 3 260 t wc 3 300 t dw 3 140 t dm 3 25 t aa 280
may 1994 24 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 read/write connections tclock this output pin is the 3.072 mhz clock output for the read and write amplifiers, it should be connected directly to the wclock pin of the write amplifier and to the rdclk pin of the read amplifier. rdmux this input pin carries the time multiplexed analog tape channel signals from the read amplifier. v ref(n) and v ref(p) these are the lower and upper voltage reference inputs for the adc in the digital equalizer part of saa3323. bias this pin defines a bias current for the adc. it should be connected to the analog supply voltage v dda via a 47 k w resistor. rdsync this output line provides synchronization information for the read amplifier data transfers. the relationship between tclock, rdsync and the channel information carried by the rdmux line is given in fig.20. this pin should be connected directly to the rdsync pin of the read amplifier. when the digital equalizer in saa3323 is in search mode this pin will be high ensuring that only the aux channel is processed by the saa3323. wdata this output pin is the multiplexed data and control line for the write amplifier. figure 21 shows the manner in which this information is multiplexed onto wdata. the wdata pin should be connected directly to the wdata pin of the write amplifier. fig.20 rdmux, rdsync and tclock timing. handbook, full pagewidth tclock rdsync rdmux ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 aux ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 aux ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 aux mgb396 fig.21 wdata and tclock timing. handbook, full pagewidth tclock wdata tdaplb mgb397 tauplb teraux tch0 tch1 tch2 tch3 tch4 tch5 tch6 tchaux tch7 sync
may 1994 25 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 tape deck capstan control connections s peed this pin outputs a pulse width modulated signal that may be used for controlling the tape capstan of the deck. operation of the speed control signal table 19 gives the sources that determine the duty factor of the speed signal. note that the 3-state speed output may be put into high-impedance state by programming the tfe setting by bit hizspd. table 19 speed signal duty factor. notes 1. tape means that the duty factor has been calculated from the played back main data tape signal. when tape is the source for the duty factor of the speed signal, the type of regulation can be chosen with the tfe settings bits enfreg and seinband. 2. m c means that the microcontroller programs the duty factor via the spddty register. 3. 50% means that the duty factor is fixed at 50%. mode m cspd source for speed duty factor dpap 0 tape (1) dpap 1 m c (2) dpar 0 tape (1) dpar 1 m c (2) drar 0 50% (3) drar 1 m c (2)
may 1994 26 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 mea717 100 % 91 % 50 % 9 % 0 duty factor speed + 2 blocks + 10.6 ms + 1.65 blocks + 8.8 ms ?2 blocks ?10.6 ms ?1.65 blocks ?8.8 ms 0 fig.22 speed regulation duty factor as a function of phase characteristic. if enfreg is programmed low then there is phase regulation of the capstan speed. the period of the pulse width modulated speed signal is 41.66 m s. the saa3323 performs a new calculation to determine the duty factor of speed once every 21.33 ms, giving a sampling rate of approximately 46.9 hz. this calculation is basically a phase comparison between the incoming main data tape frame and an internally generated reference. the speed duty factor as a function of phase characteristic is shown in fig.22. as shown the duty factor increases monotonously from approximately 9% when the incoming main data tape frame is 1.65 tape blocks (8.8 ms) too early up to 91% when it is 1.65 tape blocks (8.8 ms) too late. outside of a 2 tape blocks range the pulse width characteristic overflows and repeats itself forming a sawtooth pattern. the saa3323 has an internal buffer of 8.8 ms outside of which the phase information is invalid. if enfreg is programmed high then the above description is over-ridden with frequency information. if the incoming main data bit rate deviation from the nominal 96000 bits/s rate is less than the phase only threshold (pot) then the control is as described above in the phase control description. if the deviation is more than the frequency only threshold (fot) then the speed information is gated with the phase information resulting in the speed signal being continuously high or low while the condition continues. if the deviation is between the pot and the fot then the frequency information is gated with the phase information for 50% of the time. the deviation thresholds pot and fot are programmable via the tfe settings bit seinband. table 20 pot and fot deviation thresholds. seinband pot (deviation from nominal) fot (deviation from nominal) 0 6% 9% 1 3% 4.5%
may 1994 27 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 if sleep is high then the state of the speed signal will be the state that it was in just before the saa3323 went into sleep. thus if speed was high just before sleep it will stay high during sleep. the same applies if it was low or if it was in high-z state. note that a reset of the saa3323 will take the speed signals out of high-z state. microcontroller connections l3ref this active low output pin indicates the start of a time segment, it goes low for 5.2 m s once every 42.66 ms approximately and can be used for generating interrups for the microcontroller. if a re-synchronization occurs then the time between the occurrences van vary. this pin can be connected directly to the interrupt input of the microcontroller. l3clk this input pin is the clock line for the microcontroller interface. l3data this input/output pin is the serial data line for the microcontroller interface. l3mode this input determines the type of transfer that is occurring between the microcontroller and the saa3323. if l3mode is low then a device address can be sent by the microcontroller. if l3mode is high then a data transfer may be occurring. l3int this pin carries interrupts from the digital equalizer module. it can also be programmed to reflect the state of the aenv, label and virgin signals. table 21 timing values for fig.23. notes 1. t is the period of the master clock on the chip. 2. t d4 is the delay time between the last bit of a byte and first bit of the next byte, if no halt is used. symbol time (1) t w1 t+t su (l3mode) +t h (l3mode) ; t w1 3 200 ns t d1 t+t su (l3mode) +t h (l3clk) ; t d1 3 200 ns t h2 t+t su (l3clk) +t h (l3mode) ; t h2 3 200 ns t d2 t+t su (l3clk) +t d (l3data) ; t d2 250 ns t d5 0 t d5 50 ns t cl t+t su (l3clk) +t h (l3clk) ; t cl 3 200 ns t ch t+t su (l3clk) +t h (l3clk) ; t ch 3 200 ns t su1 t+t su (l3data) +t h (l3clk) ; t su1 200 ns t h1 t+t su (l3clk) +t h (l3data) ; t h1 35 ns t d3 2 t+t su (l3mode) +t d (l3data) ; t d3 250 ns t h3 t+t h (l3clk) +t d (l3data) ; t h3 3 50 ns t d4 2 t+t su (l3clk) +t d (l3data) ; t d4 410 ns t d4 (2) 3 t+t su (l3clk) +t d (l3data) ; t d4 575 ns
may 1994 28 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 handbook, full pagewidth mgb398 l3mode l3clk l3data microcontroller to drp l3mode l3clk l3data drp to microcontroller t d1 t cl t h1 t su1 t ch t h2 0 12 34 56 7 t h2 t w1 t d5 t d5 t d1 l3mode l3clk l3data microcontroller to drp t d1 t cl t h1 t su1 t ch 0 12 34 56 7 l3mode l3clk t d1 t cl t h3 t ch 0 12 34 56 7 l3data drp to microcontroller t d2 t d3 d4 t t d5 t h2 t h2 fig.23 l3 interface timing and typical transfers (1). a. halt mode. b. addressing mode. c. data mode (transfer from microcontroller to saa3323). d. data mode (transfer from saa3323 to microcontroller). a. b. c. d.
may 1994 29 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 handbook, full pagewidth mgb399 l3mode l3clk l3data tfe3 wcmd ldset0 tfe3 wdat set0 data tfe3 wcmd ldset1 tfe3 wdat set1 data l3mode l3clk l3data tfe3 rstat status0 data status1 data status2 data status3 data l3mode l3clk l3data tfe3 wcmd ldbycynt tfe3 wdat d8hex tfe3 wcmd rdsys tfe3 rdat sysinfo(8) l3mode l3clk l3data tfe3 wcmd status0 data l3mode l3clk l3data tfe3 rstat status0 data tfe3 rdat sysinfo(9) sysinfo(9) ldbycynt tfe3 wdat d8hex tfe3 wcmd rdsys tfe3 rstat sysinfo(8) tfe3 rdat fig.24 l3 interface timing and typical transfers (2). a. write settings bytes 0 and 1 to tfe3 part of saa3323. b. read all 4 status bytes from tfe part of saa3323. c. read 2 sysinfo bytes starting at byte 8 (in high-speed transfer part of program). d. read 2 sysinfo bytes starting at byte 8 (in low-speed transfer part of program). a. b. c. d.
may 1994 30 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 saa3323 test pins test0 to test3 these input pins are for test only, do not connect . azchk this output pin indicates the occurrence of a tape channel sync symbol on tape channels tch0 and tch7, the distance between the pulses for the tch0 and tch7 channels gives a measure of the azimuth error between the tape and head alignment. figure 25 shows the typical timing for this signal. handbook, full pagewidth mea705 (8 periods mclk) 1.3 m s this is a measure of the azimuth error. duration of the one tape block 5.3 ms azchk fig.25 azchk timing. nominal inter frame gap (ifg) lasts 660 m s. ercostat this output pin can be connected to a symbol error rate measurement system. port expansion pins pini this input pin is connected directly to the pini bit in the status byte 1, it can be read by the microcontroller, and may be used for any cmos level compatible input signals. pino1 this output pin is connected directly to the pino1 bit of the tfe settings 0 register. the microcontroller can set or reset this pin. pino2 to pino5 depending upon the type and the size of system ram used, some or all of these port expander output pins may be available, (please see section ram connections a10 and a12 to a16 on interfacing to the ram pins). supply pins v dd1 to v dd6 these are the supply pins, all of these pins must be connected. we recommend that each power supply pin pair (i.e. v dd1 to v ss1 , v dd2 to v ss2 , etc.) be decoupled using a 22 nf capacitor as close as is physically possible to the pins of the saa3323. v ss1 to v ss6 these are the supply ground pins, all of which must be connected.
may 1994 31 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 v dd7 this is the supply pin for the output buffers to the data lines of the system ram. it should always be connected externally. decouple this pin with a 22 nf capacitor to the v ss7 pin. v ss7 this is the ground supply pin for the output buffers of the data lines of the system ram. this pin is connected internally to all the supply ground pins (v ss1 to v ss6 ), however it should always be connected externally. auxiliary envelope detection intmask intmask is a interrupt mask register. this register sets the mode of operation for the interrupt interface, and is writable only. table 22 interrupt mask register. notes 1. vup o rising edge of virgin interrupt. 2. aeup o rising edge of aux envelope interrupt. 3. aedn o falling edge of aux envelope interrupt. 4. lup o rising edge of label interrupt. 5. ldn o falling edge of label interrupt. 6. ecz o aux envelope counter has just reached zero interrupt. bit 7 6 5 4 3 2 1 0 meaning bp1 bp0 vup (1) aeup (2) aedn (3) lup (4) ldn (5) ecz (6) default 0 0 0 0 0 0 0 0 bp1 and bp0 ( bypass ) if any of the bypass bits are high then the interrupts are not passed on to the microcontroller, instead the level of the corresponding signal is available an the interrupt pin. table 23 bp1 and bp0. notes 1. lab = label (high if a label condition is detected in the envelope of the aux channel). 2. aenv = envelope of the aux channel (1 bit binary). 3. vir = virgin (indicated by the total [continuous] absence of signal on the aux channel). bp effect of bypass 10 0 0 no bypass 0 1 lab on l3int pin; note 1 1 0 aenv on l3int pin; note 2 1 1 vir on l3int pin; note 3 the aux envelope information is only valid when the digital equalizer is in search mode and when the tape speed is between the values of 3to48 nominal tape speed. the timing relationships between the aux channel input signal, aenv, lab and vir are shown in figs 26 to 28. the delays t d1 and t d2 are between 0.25 and 0.5t aux (aux envelope periods). the delays t d3 , t d4 , t d5 and t d6 are between 2 and 6t aux (aux envelope periods). when using the digital equalizer in search mode first program the digital equalizer to search mode, then program the intmask register. mask if the bp1 and bp0 bits are low then the mask bits take effect. any combination of the mask bits may be high, enabling the corresponding interrupts. the interrupt pin l3int is active low when used for interrupts and active high when used for bypassing. so if it is not in bypass mode and at least one of the interrupts has occurred it will go low and stays low until deq status byte 0 has been read. extra interrupts that occur after the first interrupt and before the deq status byte 0 is read are seen in the status register. extra interrupts that occur after the status byte
may 1994 32 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 has been read will generate a new interrupt. interrupts that are already noted in the digital equalizer status 0 are cleared by reading it. table 24 digital equalizer status0. notes 1. bksw (filter bank switched) indicates that the last main data coefficients sent to the digital equalizer have been activated. 2. vup indicates whether an interrupt caused by the rising edge of virgin has occurred. 3. aeup indicates whether an interrupt caused by the rising edge of aux envelope has occurred. 4. aedn indicates whether an interrupt caused by the falling edge of aux envelope has occurred 5. lup indicates whether an interrupt caused by the rising edge of label has occurred. 6. ldn indicates whether an interrupt caused by the falling edge of label has occurred. 7. ecz indicates that the aux envelope counter has reached zero. bit 765432 1 0 meaning bksw (1) test vup (2) aeup (3) aedn (4) lup (5) ldn (6) ecz (7) fig.26 aux channel envelope to aenv delays. handbook, full pagewidth t aux rdmux aenv mgb400 d1 t d2 t fig.27 aenv to lab delays. handbook, full pagewidth aenv (internal) lab mgb401 t d3 t d4 t aux
may 1994 33 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 table 25 digital equalizer status1. notes 1. vir gives the state of the virgin signal. 2. aenv represents the state of the aenv signal. 3. lab gives the state of the lab signal. bit 76543210 meaning ----- vir (1) aenv (2) lab (3) fig.28 aenv to vir delays. handbook, full pagewidth aenv (internal) vir mgb402 t d5 t d6 t aux aux envelope count (aecnt) register this 16 bit register is used for loading the aux envelope counter and for reading the state of that counter, it is therefore readable and writable as 2 bytes. least significant byte first. table 26 aecnt register. search speed (sspd) register table 27 search speed register. notes 1. svf speed validation flag, if high then the search speed measurement is invalid. 2. sv4 to sv0 search speed value. 3. sr1 and sr0 search speed range. aecnt least significant byte most significant byte bit 7654321076543210 meaning 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 bit 76543210 meaning svf (1) sv4 (2) sv3 (2) sv2 (2) sv1 (2) sv0 (2) sr1 (3) sr0 (3) search speed 2 sr ? ?? 51.2 sv ----------- ? ?? normal speed =
may 1994 34 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 anaeye register table 28 anaeye register analog eye pattern selection register. notes 1. aen analog eye pattern output enable. if this bit is low the digital-to-analog converter (dac) is switched off and the output is high. 2. achn3 to achn0 select channel for analog eye output. table 29 achn3 to achn0 channel selections for analog eye output. t1sel register table 30 t1sel register chtst1 pin selection register. table 31 t1c3 to t1c0 chtst1 pin channel selections. bit 76543210 meaning --- aen (1) achn3 (2) achn2 (2) achn1 (2) achn0 (2) default 00000000 achn channel on anaeye 32 1 0 00 0 0 0 00 0 1 1 00 1 0 2 00 1 1 3 01 0 0 4 01 0 1 5 01 1 0 6 01 1 1 7 1 0 0 0 aux bit 765432 1 0 meaning - t1f2 t1f1 t1f0 t1c3 t1c2 t1c1 t1c0 default 0 0 0 0 0 0 0 0 t1c channel on chtst1 32 1 0 00 0 0 0 00 0 1 1 00 1 0 2 00 1 1 3 01 0 0 4 01 0 1 5 01 1 0 6 01 1 1 7 1 0 0 0 aux
may 1994 35 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 table 32 t1f2 to t1f0 chtst1 pin function selections. the digital eye pattern is in 8 bits twos complement notation, the sliced data and the bit clock give the current binary state of the corresponding signals, and the clock extraction frequency output is in 8 bits offset binary format. the timing diagrams for the digital eye pattern output and the clock extraction frequency output are shown in fig.29. t2sel register table 33 t2sel register chtst2 pin selection register. t1f function of chtst1 pin 21 0 0 0 0 off; logic 0 0 0 1 digital eye pattern 0 1 0 sliced data 0 1 1 bit clock 1 0 0 clock extraction frequency bit 7 6 5 4 3 2 1 0 meaning - t2f2 t2f1 t2f0 t2c3 t2c2 t2c1 t2c0 default 0 0 0 0 0 0 0 0 table 34 t2c3 to t2c0 chtst2 pin channel selections. t2c channel on chtst2 32 1 0 00 0 0 0 00 0 1 1 00 1 0 2 00 1 1 3 01 0 0 4 01 0 1 5 01 1 0 6 01 1 1 7 1 0 0 0 aux table 35 t2f2 to t2f0 chtst2 pin function selections. t2f function of chtst2 pin 210 0 0 0 off; logic 0 0 0 1 digital eye pattern 0 1 0 sliced data 0 1 1 bit clock 1 0 0 clock extraction frequency
may 1994 36 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 table 36 deqset digital equalizer settings. note 1. acup is the aux envelope counter direction is up. this setting caused the aux envelope counter increment or to decrement by 1 every rising edge of the aux envelope signal aenv. bit 76543210 meaning ----- acup (1) dm1 dm0 default 00000000 fig.29 chtst1 and chtst2 output timing. handbook, full pagewidth rdsync tclock chtst mclk 012345 67 0123 lsb msb mgb403 dm1 and dm0 table 37 dm1 and dm0 digital equalizer mode of operation. notes 1. in normal mode the main data channels and the aux channel are processed (equalized), the aux channel envelope information is not processed. 2. in search mode only the aux channel is processed by the digital equalizer. 3. off means that the digital equalizer is put to sleep (low power), this can be used for example in portable recording equipment. rdsync is high if off mode. also note that the other digital equalizer registers are not addressable while the digital equalizer is in off mode. dm mode of operation of digital equalizer 10 0 0 normal (1) 0 1 search (2) 1 0 off (3) 1 1 off (3)
may 1994 37 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 clkset table 38 clkset clock extraction settings. note 1. leae (leakage enable): this setting enables a leakage function in the pll clock extraction loop filter. this gives a slightly improved performance with high ser tapes at the cost of a slight decrease in dynamic performance. for home (static) applications program this bit to logic 1 and for portable applications to logic 0. bit 765432 1 0 meaning leae (1) fr1 fr0 gnor ge1 ge0 rd1 rd0 default 1 0 0 1 1 0 1 0 table 39 fr1 and fr0 clock extraction frequency range control. note that in the (fr = 0) range the clock extraction stays in its normal range only, hence it does not enter the extended range. figure 30 shows the lock characteristic of the clock extraction pll. fr effect on pll frequency loop 10 0 0 range 8% 0 1 range 16% 1 0 range 22% 1 1 range 28% table 40 gnor gain in normal frequency range mode of clock extraction. table 41 ge1 and ge0 gain in extended frequency range mode of clock extraction. gnor effect on gain in normal range 0 gain 2; for portable (mobile) applications 1 gain 1; for home (static) applications ge effect on pll gain in extended range 10 0 0 gain 2 0 1 gain 3 1 0 gain 4 1 1 gain 5; do not use fig.30 clock extraction pll lock characteristic. handbook, full pagewidth 30 20 10 0 10 4 mgb404 10 3 10 2 f (hz) bit rate deviation (%) 8% frequency loop range limitation 16% frequency loop range limitation 22% frequency loop range limitation 28% frequency loop range limitation (3) (2) (1) (1) gain 4. (2) gain 3. (3) gain 2.
may 1994 38 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 rd1 and rd0 return delay this is the delay before returning to normal mode after being in extended range mode (i.e. the number of consecutive channel clock bit periods where the bit clock frequency falls within the normal range before the clock extraction returns to normal frequency mode). table 42 rd1 and rd0 return delay. sysinfo and aux data offsets in the saa3323 aux data consists of 4 blocks of 36 bytes, one block being transferred in each (n) time segment. rd delay in bits to return to normal mode 10 0064 0 1 128 1 0 256 1 1 512 the 128 bytes in each tape frame contain sysinfo. the sysinfo bytes can for convenience, be considered as being grouped into 4 sysinfo blocks with: sysblk0 ? si0 to si31, sysblk1 ? si31 to si63, etc. in modes dpap and drar sysinfo transfers may occur in two ways: 1. 4 blocks of 36 bytes, one block being transferred to the saa3323 in each time segment. 2. 1 block of 128 bytes being transferred in time segment 1. in mode drar sysinfo must be transferred as 4 blocks of 32 bytes, one block in each segment. figures 31 to 34 show the offsets between the sysinfo and aux and the time segment counter, for the various modes of operation of the saa3323. table 43 block offsets with respect to time segment. mode description dpap sysblk = (snum + 3) mod4; or read all 4 sysinfo blocks when snum = logic 0; if aux and main were recorded simultaneously then auxblk = (snum + 1) mod4; else read and interpret 1 aux block in each time segment. drar sysblk = snum; auxblk = (snum + 1) mod4 dpar sysblk = (snum + 3) mod4; or read all 4 sysinfo blocks when snum = logic 0
may 1994 39 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 mlb413 snum aux blk 01 2 3 0123012 sys blk aux, main data input from tape 3012 123 0123012 30 123 3 0123012 3012 2301 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 01 2 3 0123012 3012 sys blk * fig.31 sysinfo and aux block delays in dpap mode; audio and aux simultaneously recorded. mlb414 snum aux blk 01 2 3 0123012 sys blk aux, main data input from tape 3012 3 0123012 3012 2301 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 01 2 3 0123012 3012 sys blk * depends on phase of aux wrt main data channels fig.32 sysinfo and aux block delays in dpap mode; audio and aux separately recorded.
may 1994 40 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 fig.33 sysinfo and aux block delays in drar mode. handbook, full pagewidth mbg405 snum aux blk 01 23 0123012 sys blk aux, main data output to tape 3012 123 0123012 30 123 3 0123012 3012 2301 01 23 0123012 3012 mlb416 snum aux blk 01 2 3 0123012 sys blk main data input from tape 3012 123 0123012 30 123 3 0123012 3012 2301 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 01 2 3 0123012 3012 sys blk * 1 0123012 3012 2301 aux output to tape fig.34 sysinfo and aux block delays in dpar mode.
may 1994 41 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 scratch pad ram the saa3323 provides the microcontroller with a scratch pad ram that the microcontroller can use for whatever it likes. the size of the scratch pad depends upon the size and type of ram used with the saa3323. the locations in the scratch pad ram may be written and read in 8 bit or 12 bit units. the ram may be viewed as having up to 4 quarters, the availability of these quarters for the scratch pad ram is given in table 44. table 44 availability of ram quarters for the scratch pad ram. note 1. in ram quarter yz = 00, the scratch pad is arranged as 6 pages, where each page consists of 7 columns 64 rows. the pages are numbered 0to5 , the columns 1to7 and the rows 0to63 . this gives a total of (6 7 64) 2688 locations. in each of the ram quarters yz = 01, 10 and 11 the scratch pad is arranged as 6 pages where each page consists of 8 columns 448 rows. the pages are numbered 0to5 , the columns 0to7 and the rows 0 to 447 . this gives then a total of (6 8 448) 21504 locations per ram quarter yz. rtype type of ram used available ram quarters yz (1) 10 0 0 dram 64k 400 0 0 dram 256k 4 00, 01, 10 and 11 0 1 sram 32k 8 fast 00 1 0 sram 128k 8 fast 00, 01, 10 and 11 1 1 sram (2 ) 32k 8 slow 00 1 1 sram 128k 8 slow 00 and 10 during communication with the scratch pad ram, the ram quarter yz is chosen when sending the rddrac, rdwdrac, wrdrac or wrwdrac commands to the tfe module. use of the scratch pad ram outside the specified ranges is not allowed and it may upset the operation of the saa3323. as with sysinfo and aux transfers can occur at high speed at all times except the second half of time segment 0, that is when the status bit slowtfr is high. when slowtfr is high the microcontroller must poll the status bit rfbt to investigate when a transfer can occur. two addressing modes are available for the scratch pad, namely random access and auto-increment. for random access mode the address of each location is sent by the microcontroller to the saa3323 before each location transfer. for auto-increment mode the address of the first location is sent by the microcontroller before the first location transfer, auto-incrementing of the row occurs then for all transfers until the end of the column. the 8 bit transfers are initiated by the wrdrac and rddrac commands, these transfers are each 1 byte per memory location, therefore the byte counter will increment after each byte transfer. the 12 bit transfers are initiated by the wrdrac and rddrac commands, these transfers are each 2 bytes per memory location. the first byte contains the 4 most significant bits (msbs) of the memory location in its 4 least significant bits (lsbs) positions. the other bit positions being dont care. the second byte contains the 8 lsbs of the memory location. the byte counter is incremented after the transfer of the second byte. the raccnt and bytcnt registers are used for addressing the scratch pad. for ram quarter yz = 00 the mapping of the scratch pad ram address onto the raccnt and bytcnt registers is shown in table 45.
may 1994 42 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 table 45 mapping of scratch pad ram address for ram quarter yz = 00. for the other three quarters of the ram the mapping of the scratch pad ram address onto the raccnt and bytcnt registers is shown in table 46. table 46 mapping of scratch pad ram address for ram quarter yz = 01, 10 and 11. register raccnt bytcnt bit 654321 07654321 0 value p2 p1 p0 c2 c1 c0 1 1 r6 r5 r4 r3 r2 r1 r0 register raccnt bytcnt bit 654321 07654321 0 value p2 p1 p0 c2 c1 c0 r8 r7 r6 r5 r4 r3 r2 r1 r0 mode changes the possible mode changes for the tfe are shown in table 47. table 47 mode changes. t iming for saa3323 mode changes mode change dpap to drar this mode change occurs at the end of the time segment in which the tfe module receives the new settings. writing of the first main and aux data to tape starts at the start of the time segment 1 which occurs 2 end of time segment 3 s after the mode change. the delay to writing to tape is approximately 222 ms, as shown in fig.35. if seamless appending is required the new settings should be sent to the tfe module during time segment 2. mode change dpap to dpar this mode change occurs at the first end of time segment 2 after the tfe module receives the new settings. output of aux to tape begins at the start of the following time segment 1, (i.e. approximately 85.3 ms after the mode change), as shown in fig.36. current mode new mode dpap drar dpar dpap - yes yes drar yes - no dpar yes no - mode change drar to dpap this mode change occurs at the first end of time segment 0 after the tfe module receives the new setting. writing of main and aux data stops immediately after the mode change.the time segment jumps back to logic 0, urda goes high and stays high for 5 time segments (i.e. approximately 213.3 ms) after which it goes low, as shown in fig.37. mode change dpar to dpap this mode change occurs at the first end of time segment 0 after the tfe module receives the new setting. the writing of aux data to tape stops immediately after the mode change. the first aux read from tape can be expected during the following time segment 0 or 1 (i.e. approximately 128 to 170.67 ms after the mode change), as shown in fig.38. mode change dpap to search this mode change occurs almost instantaneously, program the digital equalizer module in saa3323 to go to search mode, then program the interrupt mask register to select the required type of interrupt. mode change search to dpap this mode change occurs almost instantaneously, program the interrupt mask register to disable interrupts program the digital equalizer module of saa3323 to go to normal mode. a re-synchronization will most likely occur when as result of the data being read from tape, thus causing urda to go high.
may 1994 43 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 a ndbook, halfpage mea707 - 2 snum mode 01 23 0123012 new mode auxiliary, main tape out dpap drar ? 222 ms drar fig.35 mode change to drar. handbook, halfpage mea708 - 2 snum mode 123 0123012 new mode auxiliary tape out dpap dpar ? 85.3 ms dpar fig.36 mode change to dpar. handbook, halfpage mea709 - 1 snum mode 123 0 12301 new mode urda drar dpap ? 213.3 ms dpap 0 fig.37 mode change from drar. handbook, halfpage mea710 - 2 snum mode 123 0123012 new mode auxiliary tape out dpar dpap ? 128 ms dpap ? 170.66 ms auxiliary to microcontroller fig.38 mode change from dpar.
may 1994 44 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 limiting values in accordance with the absolute maximum rating system (iec 134). notes 1. the input voltage must not exceed maximum supply voltage unless otherwise specified. 2. equivalent to discharging a 100 pf capacitor through a 1.5 k w series resistor. 3. equivalent to discharging a 200 pf capacitor through a 0 w series resistor. dc characteristics v dd = 2.7 to 3.6 v; t amb = - 40 to +85 c; unless otherwise speci?ed. symbol parameter conditions min. max. unit v dd supply voltage 2.7 3.6 v v i input voltage note 1 - 0.5 v dd + 0.5 v i i input current - 10 +10 ma v o output voltage tbf tbf v i o output current - 20 +20 ma i dd supply current - 100 ma i ss supply current - 100 - ma p tot total power dissipation - 500 mw t stg storage temperature - 55 +150 c t amb operating ambient temperature - 40 +85 c v es1 electrostatic handling note 2 - 2000 +2000 v v es2 electrostatic handling note 3 - 200 +200 v symbol parameter conditions min. typ. max. unit supply v dd supply voltage 2.7 tbf 3.6 v i dd supply current digital plus analog; see fig.39 - 28.1 - ma inputs with internal pull-down to v ss ; all other inputs to v ss or v dd -- 100 m a inputs clk24, l3clk, l3mode, pini, sleep and sbmclk v il low level input voltage -- 0.3v dd v v ih high level input voltage 0.7v dd -- v i i input current v i =0vtov dd ; t amb =25 c - 10 - +10 m a inputs test0, test1 and test2 v il low level input voltage -- 0.3v dd v v ih high level input voltage 0.7v dd -- v i i input current v i =v dd ; t amb =25 c25 - 400 m a
may 1994 45 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 input reset v tlh positive-going threshold -- 0.8v dd v v thl negative-going threshold 0.2v dd -- v v hys hysteresis (v tlh to v thl ) - 0.3v dd - v outputs azchk, chtst1, chtst2, ercostat, l3int, l3ref, mclk, pino3, rdsync, sbdir, sbef, urda, tclock and wdata v oh high level output voltage i o = 1 ma v dd - 0.5 -- v v ol low level output voltage i o = - 1ma -- 0.4 v outputs a0 to a8, a9/ cas, a10/ ras, oen and wen v oh high level output voltage i o = 2 ma v dd - 0.5 -- v v ol low level output voltage i o = - 2ma -- 0.4 v outputs speed and pino2 v oh high level output voltage i o = 1 ma v dd - 0.5 -- v v ol low level output voltage i o = - 1ma -- 0.4 v i oz 3-state leakage current v i =0vtov dd ; t amb =25 c - 10 - +10 m a inputs/outputs sbcl, sbda and sbws v oh high level output voltage i o = 1 ma v dd - 0.5 -- v v ol low level output voltage i o = - 1ma -- 0.4 v v il low level input voltage outputs in 3-state -- 0.3v dd v v ih high level input voltage outputs in 3-state 0.7v dd -- v i oz 3-state leakage current v i = 0 v to v dd ; t amb =25 c - 10 - +10 m a inputs/outputs a11 to a16 and l3data v oh high level output voltage i o = 2 ma v dd - 0.5 -- v v ol low level output voltage i o = - 2ma -- 0.4 v v il low level input voltage outputs in 3-state -- 0.3v dd v v ih high level input voltage outputs in 3-state 0.7v dd -- v i oz 3-state leakage current v i = 0 v to v dd ; t amb =25 c - 10 - +10 m a inputs/outputs d0 to d7 v oh high level output voltage i o = 4 ma v dd - 0.5 -- v v ol low level output voltage i o = - 4ma -- 0.4 v v il low level input voltage outputs in 3-state -- 0.8 v v ih high level input voltage outputs in 3-state 2 -- v i oz 3-state leakage current v i =0vtov dd ; t amb =25 c - 10 - +10 m a symbol parameter conditions min. typ. max. unit
may 1994 46 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 average current consumption 2.5 60 40 20 0 3.0 3.5 4.0 mlb778 v (v) dd i dd (ma) max typ min 2.0 fig.39 average current consumption. ac characteristics v dd = 2.7 to 3.6 v; t amb = - 40 to +85 c; c l = 10 pf on all outputs; see fig.40; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit clock inputs c i input capacitance -- 10 pf clk24 f clk24 clock frequency 24 24.576 25 mhz t 24l pulse width low 12 -- ns t 24h pulse width high 12 -- ns sbmclk f sbmclk clock frequency 6.144 12.5 mhz t scl pulse width low 30 -- ns t sch pulse width high 30 -- ns
may 1994 47 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 clock output mclk c l load capacitance -- 20 pf t d delay time from sleep high to sleep active - 20 - ns f mclk clock frequency 6.144 6.25 mhz t mcl mclk pulse width low 50 -- ns t mch mclk pulse width high 50 -- ns t pd propagation delay time from rising edge of clk24 -- 65 ns inputs c i input capacitance -- 10 pf l3clk, l3mode and reset t su set-up time to rising edge of mclk 35 -- ns t h hold time from rising edge of mclk 0 -- ns pini t su set-up time to rising edge of mclk 60 -- ns t h hold time from rising edge of mclk 0 -- ns outputs c l load capacitance -- 20 pf a0 to a8 t pd propagation delay time from falling edge of clk24 -- 50 ns a9/ cas, a10/ ras and oen t pd propagation delay time from falling edge of clk24 -- 50 ns t d delay time from sleep high to sleep active - 20 - ns wen t pd propagation delay time from falling edge of clk24 -- 50 ns from falling edge of wen to rising edge of clk24 long write pulse mode -- 50 ns t d delay time from sleep high to sleep active - 20 - ns azchk, chtst1, chtst2, l3int, pino3, rdsync, sbef and wdata t pd propagation delay time from rising edge of mclk -- 45 ns ercostat, l3ref, sbdir, speed, pino2, urda and tclok t pd propagation delay time from rising edge of mclk -- 55 ns symbol parameter conditions min. typ. max. unit
may 1994 48 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 inputs/outputs c i input capacitance -- 10 pf c l load capacitance -- 20 pf a11 to a16 t d delay time from sleep high to sleep active - 25 - ns t pd propagation delay time from falling edge of clk24 -- 55 ns d0 to d3 t d delay time from sleep high to sleep active - 20 - ns t su set-up time to falling edge of clk24 5 -- ns t h hold time from falling edge of clk24 15 -- ns t pd propagation delay time from falling edge of clk24 -- 50 ns from rising edge of clk24 early write mode -- 50 ns d4 to d7 t d delay time from sleep high to sleep active - 25 - ns t su set-up time to falling edge of clk24 5 -- ns t h hold time from falling edge of clk24 15 -- ns t pd propagation delay time from falling edge of clk24 -- 50 ns from rising edge of clk24 early write mode -- 50 ns l3data t d delay time from sleep high to sleep active - 25 - ns t su set-up time to rising edge of mclk 35 -- ns t h hold time from rising edge of mclk 0 -- ns t pd propagation delay time from rising edge of mclk -- 50 ns from l3mode -- 45 ns sbcl and sbws t d delay time from sleep high to sleep active - 25 - ns t su set-up time to rising edge of mclk 40 -- ns t h hold time from rising edge of mclk 0 -- ns t pd propagation delay time from rising edge of sbmclk -- 60 ns from rising edge of mclk (3-state control) -- 55 ns symbol parameter conditions min. typ. max. unit
may 1994 49 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 sbda t d delay time from sleep high to sleep active - 25 - ns t su set-up time to rising edge of mclk 35 -- ns t h hold time from rising edge of mclk 0 -- ns t pd propagation delay time from rising edge of mclk -- 55 ns symbol parameter conditions min. typ. max. unit fig.40 timing for ac characteristics. handbook, full pagewidth mgb407 clk24 in1 out1 mclk in2 out2 sbmclk out3 v il ih v v oh v ol v il ih v v oh v ol v il ih v v oh v ol v il ih v v oh v ol d1 t d2 t pd t d4 t d5 t 24l t 24h t d t mch t mcl t su1 t su2 t sch t scl t h1 t h2 t
may 1994 50 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 adc characteristics v dd = 2.7 to 3.6 v; t amb = - 40 to +85 c; c l = 10 pf on tclock output; see fig.41; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit ac rdmux adc resolution - 8 - bits v ref(p) positive reference voltage -- v dd - 0.5 v v ref(n) negative reference voltage 0 -- v d v ref v ref(p) to v ref(n) 2.0 -- v z i input impedance v ref(p) to v ref(n) 700 1200 1500 w v ref(n) to v ss - 650 -w c i input capacitance (rdmux) -- 15 pf i i input current -- 90 m a dnl differential non-linearity -- 0.99 lsb s/(thd+n) signal-to-total harmonic distortion plus noise ratio - 20 db (fs); 100 to 500 khz 24 -- db timing t cy cycle time of clk24 40 -- ns t d1 tclock delay time from rising edge of clk24 c l =10pf -- 80 ns t su rdmux set-up time to falling edge of clk24 z source < 150 w 60 -- ns t h rdmux hold time from falling edge of clk24 40 -- ns handbook, full pagewidth clk24 mgb408 rdmux testbus clk adc tclock sample(1) v il ih v v oh v ol t su t d1 data sample(1-2) data sample(1-3) t d3 t cy t d2 t h t d4 v il ih v fig.41 adc timing.
may 1994 51 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 dac characteristics v dd = 2.7 to 3.6 v; t amb = - 40 to +85 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit digeye/anaeye resolution - 6 - bits v o anaeye output voltage z l >1m w- (v dd - 1.1) to v dd - v
may 1994 52 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 package outlines handbook, full pagewidth a b 12.1 11.9 14.3 13.7 0.15 m b 0.25 0.13 1.45 1.05 (4x) pin 1 index 1 80 61 60 41 40 20 0.25 0.13 0.5 0.15 m a 21 0.5 (4x) 1.45 1.05 12.1 11.9 14.3 13.7 s 0.1 s seating plane x mbb947 detail x 0.18 0.12 1.7 1.5 0 to 4 o 0.70 0.58 0.7 0.3 0.16 0.04 1.5 1.3 fig.42 plastic thin quad flatpack; 80 leads; body 12 12 1.4 mm (sot315-1; tqfp80). dimensions in mm.
may 1994 53 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 handbook, full pagewidth msa394 - 1 1.0 0.6 detail x 1.4 1.2 0.25 0.14 3.2 2.7 0 to 7 o 2.90 2.65 0.25 0.05 s 0.10 s seating plane x a b pin 1 index 18.2 17.6 1.0 0.6 (4x) 20.1 19.9 24.2 23.6 0.8 0.20 m b 0.45 0.30 0.45 0.30 1.2 0.8 (4x) 0.8 14.1 13.9 0.20 m a 1 80 65 24 25 40 41 64 fig.43 plastic quad flatpack; 80 leads (lead length 1.95 mm); body 14 20 2.7 mm; high stand-off height (sot318-2; qfp80). dimensions in mm.
may 1994 54 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 soldering plastic quad ?atpacks b ywave during placement and before soldering, the component must be fixed with a droplet of adhesive. after curing the adhesive, the component can be soldered. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 c within 6 s. typical dwell time is 4 s at 250 c. a modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. b y solder paste reflow reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. dwell times vary between 50 and 300 s according to method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 min at 45 c. r epairing soldered joints ( by hand - held soldering iron or pulse - heated solder tool ) fix the component by first soldering two, diagonally opposite, end pins. apply the heating tool to the flat part of the pin only. contact time must be limited to 10 s at up to 300 c. when using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 c. (pulse-heated soldering is not recommended for so packages.) for pulse-heated solder tool (resistance) soldering of vso packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.
may 1994 55 philips semiconductors preliminary speci?cation drive processor for dcc systems saa3323 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. the digital compact cassette logo is a registered trade mark of philips electronics n.v.
philips semiconductors philips semiconductors C a worldwide company argentina: ierod, av. juramento 1992 - 14.b, (1428) buenos aires, tel. (541)786 7633, fax. (541)786 9367 australia: 34 waterloo road, north ryde, nsw 2113, tel. (02)805 4455, fax. (02)805 4466 austria: triester str. 64, a-1101 wien, p.o. box 213, tel. (01)60 101-1236, fax. (01)60 101-1211 belgium: postbus 90050, 5600 pb eindhoven, the netherlands, tel. (31)40 783 749, fax. (31)40 788 399 brazil: rua do rocio 220 - 5 th floor, suite 51, cep: 04552-903-s?o paulo-sp, brazil. p.o. box 7383 (01064-970). tel. (011)821-2327, fax. (011)829-1849 canada: integrated circuits: tel. (800)234-7381, fax. (708)296-8556 discrete semiconductors: 601 milner ave, scarborough, ontario, m1b 1m8, tel. (0416)292 5161 ext. 2336, fax. (0416)292 4477 chile: av. santa maria 0760, santiago, tel. (02)773 816, fax. (02)777 6730 colombia: iprelenso ltda, carrera 21 no. 56-17, 77621 bogota, tel. (571)249 7624/(571)217 4609, fax. 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(021)577035/5874546. philippines: philips semiconductors philippines inc, 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. (02)810 0161, fax. (02)817 3474 portugal: philips portuguesa, s.a., rua dr. antnio loureiro borges 5, arquiparque - miraflores, apartado 300, 2795 linda-a-velha, tel. (01)14163160/4163333, fax. (01)14163174/4163366. singapore: lorong 1, toa payoh, singapore 1231, tel. (65)350 2000, fax. (65)251 6500 south africa: s.a. philips pty ltd., components division, 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. (011)470-5911, fax. (011)470-5494. spain: balmes 22, 08007 barcelona, tel. (03)301 6312, fax. (03)301 42 43 sweden: kottbygatan 7, akalla. s-164 85 stockholm, tel. (0)8-632 2000, fax. (0)8-632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. (01)488 2211, fax. (01)481 77 30 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1. taipeh, taiwan roc, p.o. box 22978, taipei 100, tel. (02)388 7666, fax. (02)382 4382. thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, thailand, tel. (662)398-0141, fax. (662)398-3319. turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. (0 212)279 2770, fax. (0212)269 3094 united kingdom: philips semiconductors limited, p.o. box 65, philips house, torrington place, london, wc1e 7hd, tel. (071)436 41 44, fax. (071)323 03 42 united states: integrated circuits: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. (800)234-7381, fax. (708)296-8556 discrete semiconductors: 2001 west blue heron blvd., p.o. box 10330, riviera beach, florida 33404, tel. (800)447-3762 and (407)881-3200, fax. (407)881-3300 uruguay: coronel mora 433, montevideo, tel. (02)70-4044, fax. (02)92 0601 for all other countries apply to: philips semiconductors, international marketing and sales, building baf-1, p.o. box 218, 5600 md, eindhoven, the netherlands, telex 35000 phtcnl, fax. +31-40-724825 scd31 ? philips electronics n.v. 1994 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. printed in the netherlands 513061/1500/01/pp56 date of release: may 1994 document order number: 9397 732 30011

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